1. Field of the Invention
The present invention relates to a semiconductor device in which there is formed a contact hole in a manner resulting in a structure having an improved packing density and high reliability.
2. Description of the Prior Art
As semiconductor devices become miniaturized increasing from 0.5 .mu.m to a 0.3 .mu.m packing density level, new and unanticipated problems must be overcome in the manufacturing of these devices. Such problems include dealing with unexpected physical properties of higher density semiconductor circuits and limitations posed by existing processing methods and manufacturing equipment and facilities.
Increased packing density is particularly a cause of reduced reliability in connection with fabrication of MOS transistors. The reduction of channel length and the size of the field oxide layer regions contribute to both a short-channel effect and the well known punch-through phenomenon thereby imposing limits in the manufacturing of high density semiconductor devices.
FIG. 1A shows a layout of a semiconductor device which illustrates a conventional method for forming a contact hole in a semiconductor device.
FIG. 1B shows a cross-section of the semiconductor device of FIG. 1A cut along line AA. In FIG. 1A, mask pattern P1 rectangular regions are horizontally symmetrical and form a field oxide layer to divide a semiconductor substrate into an active region and a device isolating region. Mask pattern P2 square regions which exist inside mask pattern P1 and have two crossing oblique lines form a contact hole which interconnects a conductive layer to an impurity diffusion region. Mask pattern P3 regions which include mask pattern P2 and are shown extending in different directions form a conductive layer. L.sub.5 represents the narrowest width of a field oxide layer, L.sub.s represents the shortest distance between the second impurity diffusion regions, L.sub.11 represents the shortest distance between the contact holes, D represents a second impurity region and L.sub.OL represents the width of a portion which is overlapped when the second impurity diffusion regions are horizontally extended.
FIG. 1B illustrates a semiconductor device which comprises a field oxide layer 12 for dividing a semiconductor substrate 10 of a first conductivity type into a device isolating region and an active region, a first impurity diffusion region 100 of a second conductivity which is formed in the active region, a second impurity diffusion region 200 of a second conductivity which is formed in the first impurity diffusion region, an interlayer insulator 1B which isolates the substrate 10 from a conductive layer 50, a contact hole 300 formed in the interlayer insulator 18 for electrically connecting conductive layer 50 to second impurity diffusion region 200, and conductive layer 50.
The second impurity diffusion region 200 of a second conductivity is formed so as to both reduce contact resistance between the conductive layer 50 and substrate 10 and to prevent operation failure of the device by etching deeper than the depth of the first impurity diffusion region 100 due to the overetching of the substrate during the dry etching for forming the contact hole. Usually, the impurity concentration of the second impurity diffusion region 200 is higher than that of the first impurity diffusion region 100, and the junction depth of the second impurity diffusion region 200 is deeper than that of the first impurity diffusion region 100 (junction depth is the depth of an impurity diffusion region from the surface of a substrate).
The second impurity diffusion region which is formed of impurity ions doped through the contact hole is spread laterally by thermal energy supplied to the substrate during a process of doping the impurity ions or during other subsequent processes, which reduces the effective iHxlating interval of the device isolating region and results in short-channel effect and punch-through.
In FIG. 1B, the effective device isolating interval L.sub.1 measured before the formation of the second impurity diffusion region 200 is then reduced by .DELTA.L compared to the effective device isolating interval L.sub.2 measured after the formation of the second impurity diffusion region. This is true given that .DELTA.L/2 represents the length that the device isolating region is laterally eroded by one second impurity diffusion region, and that the impurity ions of both the two second impurity diffusion regions have the same lateral diffusion condition.
The reduction of the effective device isolating interval does not present a great a great problem in a relatively large device isolating region whose area is for example, about 0.8 .mu.m as in a 16 Mb DRAM. However, in a small device isolating region whose area is for example, about 0.5 .mu.m as in a 64 Mb DRAM, the reduction of the effective device isolating interval deteriorates the reliability of the device.